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SCC Drivers
HDLC860 Driver
Features include:
- Supports TargetLAPBTM, Blunk Microsystems' ISO/IEC 7776 compliant LAPB protocol stack. May also be used as a stand-alone HDLC frame driver or with other upper layer protocols.
- Interrupt driven and DMA driven to reduce overhead and maximize throughput.
- Baud rate and line signal monitoring are configurable at run-time. The
transmit and receive clocks are independently configured as either
externally or internally generated.
- Contains watchdog timer to detect external transmit clock failures. Detects
if outbound packets take excessive time to complete transmission.
- Supports control of the RTS and DTR output signals and monitoring of the
CTS, DCD, and DSR input signals.
- Supports one SCC channel at speeds up to 20 Mbps using a 50 MHz MPC860.
Multiple copies of the driver can be used to support multiple channels.
- Configurable for either NRZ or NRZI data encoding.
- Statistics counters are maintained on the number of received ABORTs, CRC
errors, overrun errors, short frames, long frames, and byte alignment
errors. Statistics values can be read or printed to stdout.
- Includes two sample applications, one using TargetLAPB and another that operates stand-alone.
- Extensively tested with TargetLAPB.
- Integrated with TargetOSTM, Blunk Microsystems' full-featured royalty-free RTOS.
- Developed and tested using TargetTools™, the IDE for embedded development from Blunk Microsystems with an integrated compiler and kernel-aware debugger, visual code editor, search and replace tool, BDM for board bring-up, and fast Ethernet download.
- Royalty free. Includes source code, manual, sample applications, and one
year of technical support.
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